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Package more information
The wafer level CSP is ultra small and thin package developed to meet the requirements for high performance and downsizing typically by mobile equipment.
LAPIS Semiconductor provides strong support for customers' excellent product development by carrying out development based on the package technology cultivated for our own semiconductor devices and expanding foundry services for cutting-edge packages.
Achieved ultra small packages ; 0% in mounting area and 10% in weight*1compared with conventional packages
*1 : Compared with LAPIS Semiconductor's 100-pin TQFP
TQFP and WCSPQFP/WCSP
Ultra Thin Type
- Achieved 0.3mm thickness (typ.) for LGA. 0.4mm thickness (typ.) is also possible.0.2mm typ.
Ease of Handling
- The plastic sealing on the device surface enables installation with batch reflow equipment in the same way as for existing packages.
- Excellent reflow resistance ( JEDEC level 1 ) is achieved with material/process technologies.
- The control of wiring width and wiring length enables achievement of excellent electrical characteristics.
Semiconductor devices for compact and light-weight equipment such as mobile phones, smart phones, digital camera.
Reliability Evaluation Results for Reference
|High-temperature operation test (Ta : 125°C、VDD : 3.6V)||1000H Pass|
|High-temperature storage test (Ta : 150°C)||1000H Pass|
|High-temperature high-humidity bias test (Ta : 85°C、RH：85%、VDD：3.6V)||1000H Pass|
|Vapor unsaturation pressure test (Ta : 121°C、RH : 85%)||300H Pass|
|Temperature cycle test (-65°C to RT to 150°C)||500cyc. Pass|
|Wafer diameter||6 in., 8 in.|
|Pin material||Eutectic , Pb-free|
For customers to accelerate development and achieve volume production target, LAPIS Semiconductor provides strong supports:
- Quick response through direct access to our key persons for individual items.
- Support for heat resistance analysis and electrical characteristics analysis