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AS@P2ROM™ series with Built-In Gate Array (Application Specific P2ROM™)

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AS@P2ROM with Built-In Gate Array

Description

AS@P2ROM™ incorporate a P2ROM core with a gate array on a single chip. Security functions can be added and the interface customized to meet set needs by gate array. The lineup includes medium speed and high speed types up to 1Gbit and 128Mbit, respectively.

Line-up

Design interface can support any interface (specification / RTL / Netlist)
Part No. Supply
voltage
(V)		 Memory
density
(bit)		 Configu
-ration
(word
×bit)		 Function Access
time
Random
/Page
(ns)		 Standby
current
consump
-tion
(Max.)		 Package
NEW
MR35V01G7□B		 3.0 to 3.6 1G 128M×8 Gate Array 30K Gate (typ.) built-in
3 input & 8 inout		 920/320 10µA TSOP(I)48
NEW
MR35V5127□B		 3.0 to 3.6 512M 64M×8 Gate Array30K Gate (typ.) built-in
26 input & 8 inout		 240/25 10µA TSOP(II)44
NEW
MR35V2567□B		 3.0 to 3.6 256M 32M×8 Gate Array 30K Gate (typ.) built-in
3 input & 8 inout		 920/320 50µA TSOP(II)44
MR25T1287□L 2.7 to 3.6 128M 8M×16
16M×8		 Gate Array 25K Gate (typ.) built-in
26 input & 16 inout		 80 to 100/25 10µA TSOP(I)48
TSOP(II)44
MR25T647□L 2.7 to 3.6 64M 4M×16
8M×8		 Gate Array 25K Gate (typ.) built-in
26 input & 16 inout		 80 to 100/25 10µA TSOP(I)48
TSOP(II)44
MR25T167□L 2.7 to 3.6 16M 1M×16
2M×8		 Gate Array 25K Gate (typ.) built-in
26 input & 16 inout		 70 to 100/25 50µA TSOP(I)48
TSOP(II)44
MR25T1671L 2.7 to 3.6 16M 1M×16
2M×8		 Password authentication 70/25 50µA TSOP(I)48

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