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 >  LSI Package > Package more information FBGA,FLGA


Package more information

FBGA,FLGA

Features

Packages where a semiconductor chip is mounted on the glass epoxy substrate and is sealed with transfer mold after circuit wiring by wire bonding.

The pins are arranged on the bottom surface of the substrate in an area form.

LAPIS Semiconductor recommends FLGA using solder / Pb-free coated pins for packages with an external size of 10mm or less and FBGA using solder/Pb-free balls with an external size exceeding 10mm.

In each package, MCP (Multi Chip Package) using lamination structure can also be supported.

Lineup

 

FBGA family


PKG
Size
Pin Count Pin
Pitch
Pin
Arrangement
PKG
Code
Status
6×6
mm
60 0.5
mm
2rows in periphery P-LFBGA
64-0606-0.50
Volume production
7×7
mm
48 0.8
mm
2rows in periphery P-LFBGA
48-0707-0.80
8×8
mm
160 0.5
mm
4rows in periphery P-TFBGA
160-0808-0.50
9×9
mm
84 0.8
mm
3rows in periphery P-LFBGA
84-0909-0.80
9×9
mm
120 0.65
mm
3rows in periphery P-TFBGA
120-0909-0.65
11×11
mm
144 0.8
mm
4rows in periphery P-LFBGA
144-1111-0.80
11×11
mm
176 0.65
mm
4rows in periphery P-LFBGA
176-1111-0.65
13×13
mm
144 0.8
mm
3rows in periphery P-LFBGA
144-1313-0.80
13×13
mm
224 0.65
mm
4rows in periphery P-LFBGA
224-1313-0.65
15×15
mm
224 0.8
mm
4rows in periphery P-LFBGA
224-1515-0.80
 

FLGA family


PKG
Size
Pin Count Pin
Pitch
Pin
Arrangement
PKG
Code
Status
7×7
mm
48 0.8
mm
2rows in periphery P-TFLGA
48-0707-0.80
Volume production
8×8
mm
56 0.8
mm
2rows in periphery P-TFLGA
56-0808-0.80
9×9
mm
84 0.8
mm
3rows in periphery P-TFLGA
84-0909-0.80

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